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| Datasheet File OCR Text: |
| geometry process details principal device types cbcp68 CBCX68 cmpt651 czt651 mps650 mps651 gross die per 5 inch wafer 10,583 process cp314v small signal transistor npn - high current transistor chip process epitaxial planar die size 40 x 40 mils die thickness 7.1 mils base bonding pad area 7.9 x 8.7 mils emitter bonding pad area 9.0 x 14 mils top side metalization al - 30,000? back side metalization au-as - 13,000? www.centralsemi.com r1 (22-march 2010)
process cp314v typical electrical characteristics www.centralsemi.com r1 (22-march 2010) |
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